The organic LED (light-emitting diode) display, a type of flat panel display, is a recent focus of attention as a competitor of the liquid crystal display. A great deal of efforts are put into the development of display circuits and driving methods for the organic LED display.
Drive circuits and methods for use with the organic LED display are divided into two major categories: passive and active. To apply the active drive technology to organic LED displays, those TFT which drive the pixels have to be made of polysilicon.
This is because when self-luminous elements are to be driven by TFTs as in the organic LED display, sufficient movement is required with electric charges in the silicon forming the TFTs to ensure an amount of current flow through the self-luminous elements. This explains why polysilicon is needed in the organic LED display, while amorphous silicon is sufficient in the non-light-emitting shutter element, such as liquid crystal.
U.S. Pat. No. 4,996,523 (issued Feb. 26, 1991) discloses a pixel configuration of the organic LED display based on monocrystalline silicon TFTs instead of polysilicon TFTs, in particular, a configuration using memory elements.
FIG. 26 shows a circuit configuration in a single pixel (precisely, should be termed “a single dot” because 1 pixel=1 dot in a black & white display and 1 pixel=RGB 3 dots in a color display; however, no strict restrictions are made here).
According to U.S. Pat. No. 4,996,523, as shown in FIG. 26, each pixel is formed by: multiple memory cells 221 or Cn to Cn-3; transistors 222 or Dn to Dn-3; to select from those memory cells; a constant current circuit 225; and an organic LED element 226.
The constant current circuit 225 is a current mirror circuit including FETs 223, 224. Therefore, the current through the organic LED element 226 is determined by the total current flow in the FETs Dn to Dn-3. The current flow in the FETs Dn to Dn-3 is specified by the gate voltages of the FETs Dn to Dn-3 which are determined by the data stored in the memory cells Cn to Cn-3.
The configuration of the memory cells 221 is shown in FIG. 27. Specifically, a CMOS inverter 228 and MOS transmission gates 227, 229 are controlled by means of a LOW control signal. When the LOW control signal is in a selection state, the MOS transmission gate 227 is in a conducting state, and the MOS transmission gate 229 is in a non-conducting state; therefore, a column input signal Bn is fed to the gate of a CMOS inverter 230 via the MOS transmission gate 227. When the LOW control signal is in a non-selection state, the MOS transmission gate 227 becomes non-conducting, and the MOS transmission gate 229 becomes conducting; therefore, the output from a CMOS inverter 231 is fed back to the CMOS inverter 230 via the MOS transmission gate 229. In the memory cell 221, the output from the CMOS inverter 230 is fed back to the gate of the CMOS inverter 230 via the CMOS inverter 231 and the MOS transmission gate 229; the circuit can be therefore regarded as being a static memory circuit with two-stage inverters.
This way, U.S. Pat. No. 4,996,523 discloses a memory structure including monocrystalline silicon TFTs, as a pixel-TFT configuration for use with the organic LED display.
The aforementioned pixel memory structure disclosed in U.S. Pat. No. 4,996,523 (see FIG. 26) includes multiple memory cells Cn to Cn-3, as well as a current mirror circuit 225, in each pixel to convert a digital signal to an analog signal (current value) by means of the current mirror circuit.
The structure including a current mirror circuit requires its components, the FETs 223, 224, to have identical characteristics; however, fabricating the FETs by a polysilicon process, which is used for fabrication of liquid crystal displays for example, does not guarantee identical characteristics between neighboring FETs.
As a result, the circuit for an analog gray-scale method in FIG. 26 entails a problem of irregular characteristics in polysilicon TFTs and can produce a homogeneous gray-scale display across the entire screen only with difficulties.
Accordingly, it is suggested to restrain irregularities in polysilicon TFT characteristics by the adoption of digital gray-scale techniques. FIG. 33 shows a pixel circuit structure for use in a time-ratio gray-scale method, a kind of those digital gray-scale method techniques. Specifically, the structure includes a TFT 107 which drives an organic LED display 108, a capacitor 119 which builds voltage accumulation to control the conduction of the TFT 107, and a TFT 106 to control the voltage applied to the capacitor 119. In this structure, the method rewrites the voltage applied to the capacitor 119 in the pixel several times in a single frame period TF as shown in FIG. 34 and produces a gray-scale display by setting the voltage to either such a value that causes the TFT 107 to conduct or such a value that causes the TFT 107 to not conduct.
Japanese Unexamined Patent Application 8-194205 (Tokukaihei 8-194205/1996; published on Jul. 30, 1996) discloses a configuration of a liquid crystal display, in which a static memory structure is incorporated in every pixel by means of a polysilicon TFT.
Referring to FIG. 28, in Tokukaihei 8-194205, there are pixel electrodes 202 arranged in a matrix on a first glass substrate, and a scan line 203 running horizontally and a signal lines 204 running vertically between every pair of adjacent pixel electrodes 202. Also, reference lines 205 are provided in parallel to the scan lines 203. At every crossing of the scan lines 203 and the signal lines 204, a memory element 206 (detailed later) is provided, and a switching element 207 is provided between the memory element 206 and the pixel electrode 202.
A second glass substrate is provided to oppose the first glass substrate at a predetermined distance. The second glass substrate has opposite electrodes on a side facing the first glass substrate. A liquid crystal layer as a display material layer is sealed between the two glass substrates. In FIG. 28, 208 is a scan line driver, 209 is a signal line driver, and 210 is a reference line driver.
FIG. 29 is a circuit diagram showing the structure of a pixel portion in FIG. 28. A binary data recording memory element 206 is connected to each of the crossings, of the scan lines 203 and the signal lines 204, arranged in a matrix. The memory element 206 has an output section for outputting stored information. A TFT 214, as a three-terminal switching element 207, is connected to the output section. The switching element 207 controls the resistance between the reference lines 205 and the pixel electrodes 202 to adjust the bias applied to the liquid crystal layer 215.
In FIG. 29, a static memory element is used as the memory element 206. The static memory element is a memory circuit which delivers a positive feedback by means of two-stage inverters. Consequently, the data fed through the signal lines 204 is supplied to the gate terminal of the inverter 212 when the TFT 211 is conducting. The output from the inverter 212 is resupplied to the gate terminal of the inverter 212 via the inverter 213; therefore, when the TFT 211 conducts, the data supplied to the inverter 212 is fed back to the inverter 212 without changing the polarity thereof and stored until the TFT 211 conducts next time.
This way, Tokukaihei 8-194205 discloses a memory structure including polysilicon TFTs, as a pixel-TFT configuration for use with the liquid crystal display. The TFT substrate structure disclosed in the Tokukaihei as shown in FIG. 29 includes a static memory 206 for every pixel and produces a binary display from data stored in the pixel memory.
Japanese Unexamined Patent Application 2000-227608 (Tokukai 2000-227608; published on Aug. 15, 2000) discloses a circuit structure for a liquid crystal display in which an exterior of a display section has a memory function.
FIG. 30 is a block diagram showing the structure of a display substrate disclosed in the document.
According to Tokukai 2000-227608, a display section 310 on the display substrate is connected to an image memory 308 via line buffer 309. The image memory 308 includes memory cells arranged in a matrix and has a bitmap structure sharing a common address space with those pixels in the display section 310. An address signal 303 is supplied via a memory control circuit 306 to a memory line selector circuit 311 and a column selector circuit 307. The memory cell address by the address signal 303 is selected by a column line and a line wire (not shown) so that display data 304 is written to the memory cell. After the writing, data for a single line including the selected pixel is transmitted to the line buffer 309 by an address signal supplied to the memory line selector circuit 311. Since the line buffer 309 is connected to signal wiring (not shown) of the display section, the read-out data is transmitted to the signal wiring.
The address signal is also supplied to an address line converter circuit 305 so as to apply the selected voltage to line selector wiring (not shown) by means of a display line selector circuit 312
This operation results in the writing of the data in the image memory 308 to the display section 310.
The pixel circuit structure of the display section 310 is shown in FIG. 31. A control TFT 405 is controlled with a line selector wire 401, the data supplied from a signal wire 402 is stored in a capacitor 406 located between a common wire 404 and the control TFT 405, conduction (and non-conduction) of a drive TFT 409 is controlled by the voltage across the capacitor 406, and it is determined whether to apply a voltage supplied to a display electrode 408 from a liquid crystal standard wire 403. A correction capacitor 409 is connected between the source and drain terminals.
FIG. 32 shows another pixel circuit structure of the display section 310. The TFT drives liquid crystal using an analog switch 504. To drive the analog switch, which is composed of a pch TFT and a nch TFT, two sets of memory circuits are provided, each set including a sampling capacitor 503, 507 and a sampling TFT 502, 506. Data items of different polarities are supplied via two data wires 501, 505, connected to a common line selector wire 401, and simultaneously sample to produce a display.
The document also discloses that the data items with different polarities which drive the analog switch can be produced by an inverter circuit built inside a pixel, instead of the provision of two sets of memory circuits, and that the memory circuit used for semiconductor as a memory circuit is constructed around a TFT.
This way, Tokukai 2000-227608 discloses the configuration of a polysilicon TFT substrate for a liquid crystal display. The configuration is such that the TFT substrate structure shown in FIG. 30 includes, outside the display section 310 the image memory 308 composed of an SRAM, the display section 310 includes pixel memories constructed around a capacitor as shown in FIGS. 31 and 32, and a display is produced from binary data stored in the pixel memories.
As mentioned in the foregoing, it is suggested to restrain irregularities in polysilicon TFT characteristics by the adoption of digital gray-scale method techniques. However, the time-ratio gray-scale method could probably entail the development of moving picture breakup (dynamic false contours) as is the case with PDPs (plasma display panels). The moving picture breakups develop according to the following mechanism (see FIG. 35). The eye moves as indicated by broken lines (a)-(d) when the pattern of tone level 32 moves on the background of tone level 31 and can recognize a tonal pattern formed by those pixels on the lines at the time of the eye passing over them. For example, along broken line (a), the eye movement coincides with a light-on timing of tones 1, 2, 4, 8, 32 so that the eye can see tone level 47. Along broken line (d), the eye movement coincides only with the light-on timing of tone 16 so that the eye can see tone level 16.
Accordingly, in the PDP and other pieces of apparatus, the animated-image moving picture breakup is improved by dividing large bit-weight data into several sets and displaying those sets before or after small bit-weight data. In other words, the moving picture breakup is reduced by large bit-weight data which appears several times in a cycle of a certain frame period.
However, to produce a display from that large bit-weight data several times on a PDP, etc. scanning is necessary for every display.
Further, U.S. Pat. No. 4,996,523 mentions that the circuit shown in FIG. 26 is provided to each pixel. To compete with recent developments of liquid crystal displays which have achieved a 64 gray-scale method, the PDP requires a 6-bit memory for each pixel. However, in a normal display, three (RGB) pixels are accommodated in a limited space of about 150 [μm]×150 [μm]−300 [μm]×300 [μm], in which there must be further provided a gate wire, source wire, power source wire, etc, as well as a 6-bit memory circuit arranged as shown in FIG. 26. This is not easy even with a present low-temperature polysilicon process. Building more than 3-bit memory wold be impossible. When this is the case, the device can produce a maximum of only 8 tones and lacks appeal as a commercial product.
Meanwhile, according to Tokukaihei 8-194205, each pixel is provided with only 1-bit memory. Although this is feasible with a present low-temperature polysilicon process, a resultant still image is only binary (of multicolor owing to RGB colors), because the device relies on the 1-bit memory in producing a still image display.
Note that Tokukai 2000-227608 is free from these problems, since the memory is located outside the pixel (display region). Nevertheless, locating the memory outside the display region requires an additional area on the display substrate, which means a smaller number of substrates fabricated from a glass substrate (of an equal display area) in a TFT process and an increased manufacturing cost for a substrate of an equal display area.
We presume that the biggest advantage in imparting a memory function to the substrate is power saving, which would give the device the most competitive edge in the portable device market than in other markets. However, the above technique is not still preferable in the portable device market where miniaturization and light weight are the key factors, since a larger substrate size is required to produce an equal display area.